All forum topics Previous Topic Next Topic. Thanks for help! All PMs will be ignored Any approach will require that you have a good understanding of both VHDL and verilog. Just out of curiosity, why convert it. You can easily instantiate verilog in VHDL. Overloaded operators, complex data types, etc Just watch out for loose type matching in the verilog code. Known Limitations:.
Search the forum 2. Unknown 26 October at Unknown 15 February at Farhath 22 February at Anonymous 6 March at Anonymous 10 December at Newer Post Older Post Home. Subscribe to: Post Comments Atom. In other cases, a single assignment should be used when an object is created. Subsequent value changes are then achieved by modification of an existing object. This technique should be used for Signal and intbv objects. Signal assignment in MyHDL is implemented using attribute assignment to attribute next.
Value changes are thus modeled by modification of the existing object. The converter investigates the Signal object to infer the type and bit width of the corresponding Verilog or VHDL object. Type intbv is likely to be the workhorse for synthesizable modeling in MyHDL.
An intbv instance behaves like a mutable integer whose individual bits can be accessed and modified. Also, it is possible to constrain its set of values. In addition to error checking, this makes it possible to infer a bit width, which is required for implementation.
As noted before, it is not possible to modify value of an intbv object using name assignment. In the following, we will show how it can be done instead. This is an intbv object with initial value 0 and bit width 8. To change its value to 5 , we can use slice assignment:. Often the new value will depend on the old one. For example, to increment an intbv with the technique above:.
Python also provides augmented assignment operators, which can be used to implement in-place operations. These are supported on intbv objects and by the converter, so that the increment can also be done as follows:. For some tasks, such as debugging, it may be useful to insert arbitrary Python code that should not be converted. MyHDL provides a way to include user-defined code during the conversion process.
There are special function attributes that are understood by the converter but ignored by the simulator. They operate like a special return value. When defined in a MyHDL function, the converter will use their value instead of the regular return value. Effectively, it will stop converting at that point. The converter will substitute the appropriate values in the string and then insert it instead of the regular converted output.
There is one more issue with user-defined code. Normally, the converter infers inputs, internal signals, and outputs. It also detects undriven and multiple driven signals. To do this, it assumes that signals are not driven by default. It then processes the code to find out which signals are driven from where. Proper signal usage inference cannot be done with user-defined code.
Without user help, this will result in warnings or errors during the inference process, or in compilation errors from invalid code. The user can solve this by setting the driven or read attribute for signals that are driven or read from the user-defined code. These attributes are False by default. The latter two values specifies how the user-defined Verilog code drives the signal in Verilog.